1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Related Background Art
As for the conventional 1T-1C (one transistor-one capacitor) DRAM cell, its fabrication is becoming difficult as it becomes finer. As an alternative memory cell, an FBC (Floating Body Cell) is proposed. In the FBC, an element unit for storing one bit information is formed of one MIS (Metal Insulator Semiconductor) FET. Therefore, the occupation area of one cell is small. According to the FBC, therefore, memory elements having a large capacity can be formed in a unit area.
The conventional FBC is connected to a sense amplifier via a bit line selection circuit. Therefore, the bit line selection circuit selects one bit line from among a plurality of bit lines (for example, eight bit lines), and a sense amplifier detects data from the selected bit line as described in T. Ohsawa et al., “Memory Design Using One-transistor Gain Cell on SOI,” IEEE ISSCC (International Solid-State Circuits Conference), February 2002 (hereafter referred to as Non-Patent Document 1). Such a configuration is based on that data can be read out from a memory cell nondestructively. In other words, it has been considered that data of memory cells that are included in memory cells connected to a selected word line and that are not subjects of data readout remain unchanged from their states preceding the selection, when the word line has restored to its data holding level again without destroying the data.
However, it has been found that the charge pumping phenomenon affects memory cell data. The charge pumping phenomenon is a phenomenon that holes gradually disappear at an interface between a body surface and a gate insulation film when an inversion state and an accumulation state at the body surface of the memory cell are repetitively generated by raising and lowering the voltage on the word line as described in S. Okhonin et al., “Principles of Transients Charge Pumping on Partially Depleted SOI MOSFETs,” IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 5, MAY 2002 (hereafter referred to as Non-Patent Document 2). The number of holes that disappear due to one state change of inversion and accumulation depends on a density Nit of an interface level between the body surface and the gate insulation film and an area S of the interface. For example, supposing that Nit=1×1010 cm−2, and W (channel width)/L (channel length) of a memory cell transistor=0.1 μm/0.1 μm, S=W*L=1.0×10−10 cm2 and the number (Nit*S) of interface levels becomes approximately one. The number of holes stored in the body region of the FBC of this generation has a difference of approximately 1,000 depending upon whether the data is “1” or “0.” If the voltage raising and lowering on the word line are conducted approximately 1,000 times, therefore, data “1” completely changes to data “0.” As a matter of fact, if the voltage raising and lowering on the word line are conducted approximately 500 times, then the risk that the data “1” will be erroneously detected becomes high.
In this way, the FBC is neither a destructive read-out cell nor a complete non-destructive read-out cell. The FBC is so to speak a “quasi non-destructive read-out cell.”
Therefore, a semiconductor memory device, which is capable of preventing the charge pumping phenomenon of the FBC memory with low power consumption, is demanded.